Title: CAVP: Computer Architecture and Virtual Prototyping
Short Code: MTE7905
ECTS Credits: 2
UAS: BFH
Organizer Details: BFH HuCE
Evaluation:

Final exam 2 weeks after the last course session. The lecture will provide additional information at the beginning of the course.


Decision Date: 1 February 2024 
Start Date: 23 February 2024 
End Date: 4 April 2024 
Date Details:

Date KW SW HS23 morning (4L) HS23 afternoon (4L)
23.02.24 8 1 CAVP CAVP
01.03.24 9 2 CAVP CAVP
08.03.24 10 3 CAVP CAVP
15.03.24 11 4 CAVP CAVP
22.03.24 12 5 Self-study
29.03.24 13 6 Self-study
05.04.24 14 7 Self-study Exam CAVP
Type:

Full day course at 6 Fridays per semester + 1.5 to 2.5 days individual preparation for the exam.

The exam date, time and agenda will be fixed and announced by the lecturer at the beginning of the seminar. These details are binding.

Language(s):

English by default, but deviations according to the wishes of the students.

Description (max. 300 characters):
This course is part of the HuCE EVA course series. The course topics are Virtual Prototyping Using SystemC and Computer Architecture.
Contents and Learning Objectives:

Virtual Prototyping Using SystemC (Prof. Dr. Torsten Maehne)

This course block introduces virtual prototyping of embedded systems using SystemC. Different models of computations are presented, which are needed to efficiently model and simulate today's complex and heterogeneous hardware/software systems and their interaction with the environment at different levels of abstraction (Register Transfer Level (RTL), Bit Cycle Accurate (BCA), Transaction Level (TL)). Based on hands-on exercises, modeling and debug strategies as well as design and verification methodologies for hardware/software co-design will be discussed.

Computer Architecture (Prof. Dr. Theo Kluter)

This course block gives a broader insight in computer architectures by visiting the different types of processors, like RISC, VLIW, DSP, and GPU and their typical applications/short comings. Furthermore, the advantages and disadvantages of different memory models (shared-memory, distributed memory, caches and scratchpads) are discussed. Finally, memory coherence and consistence problems are shown with their solutions (coherence protocols in hard-/software and more advanced techniques like transactional memory models) are shown. The course closes with a brief overview of energy consumption and reduction.

Admission:
Literature:
Conditions:

50% theory and 50% labs

Contact:
  • For administrative questions and module enrolment, please contact the BFH MSE office directly. mse@bfh.ch
  • Students who are not enrolled at BFH must first create a guest account and then send an email to the BFH MSE office. Link to registration form!
  • Lecturer: Prof. Dr. Torsten Mähne and Prof. Dr. Theo Kluter
 
Contact Person E-Mail: torsten.maehne@bfh.ch
Status: cancelled
 
Specialization: Industrial Technologies (InT)

Information and Communication Technologies (ICT)

Computer Science (CS)

Electrical Engineering (ElE)

Mechatronics & Automation (MA)

Medical Engineering (Med)

 

[Responsible for this text: Mähne Torsten]